Overview

A PoC  has been proposed in Rel G timeframe to demonstrate the possibility to adopt a model driven approach in the definition of a control loop and its components using a common catalogue for any control loop artifacts and a common format and language for these artifacts (using TOSCA).

Interested to get more information or contribute ?  

Key contacts: Michela Bevilacqua ; Liam Fallon ; Fei Zhang (Ericsson)

Goals

• Demonstrate Control loops can be defined and deployed using TOSCA
• Use a design time catalogue for Control Loops for a complete storage of all the artifacts from different DT systems
• Show design time systems can populate the Design Time control loop catalogue

-DCAE-MOD interacting with the design time catalogue

-SDC interacting with the design time catalogue

• Show TOSCA defined control loops being onboarded and deployed

Longterm Roadmap

"Knowledge" is a key component for automation and control loops. 

A common knowledge can be used for Monitor, Analyze, Plan and Execute functions.

In Rel G we want to start to address in a PoC the aspect of the catalogue where multiple ONAP components could be involved in the Design Time phase.

A longterm strategy needs to apply the common "knowledge" concept to the entire Control Loop Lifecycle.  

Business Requirements

Participating Companies

Ericsson

AT&T

Contributions

Metadata Driven Control Loops

• Presentation to ARCHCOM (2020/07/14)
• Presentation to SDC project (2020/07/06)
• Presentation to ONAP TSC 2020/07/02 –>ControlLoopTOSCA_DTCatalogue_TSC_2020_07_02.pdf
• Inputs to Control Loop Subcommittee 2020/07/01:

DCAEMOD_CLAMP and Policy interworking_2020_07_01.pptx

cloop_dcae_2020_07_01.zip

• LFN DDF presentation 2020/06/25 → ControlLoopTOSCA_DTCatalogue_DDF_2020_06_25.pptx
• Input to Control Loop Subcommittee 2020/06/17 → ControlLoopTOSCA_DTCatalogue_DDF_2020_06_25.pptx

Impacts

Release requirement for this PoC in Rel G: REQ-402

Jira tracking in ARCHCOM: ONAPARC-605 

PoC is hosted by CLAMP project

Project Commitment