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| This page describes the TOSCA Control PoCs executed in the Guilin and Honolulu releases. Please refer to the TOSCA Control Loops in CLAMP (Not current, see ONAP Documentation) wiki page for the development work in Istanbul. |
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Details of the demo for this PoC are available here: Participant Full Pipeline PMSH Deployment Demo - How to run... |
Overview
A PoC has been proposed in Rel G timeframe to demonstrate the possibility to adopt a model driven approach in the definition of a control loop and its components using a common catalogue for any control loop artifacts and a common format and language for these artifacts (using TOSCA).
Interested to get more information or contribute ?
Key contacts: Michela Bevilacqua ; Liam Fallon ; Fei Zhang (Ericsson)
Goals
- Demonstrate Control loops can be defined and deployed using TOSCA
- Use a design time catalogue for Control Loops for a complete storage of all the artifacts from different DT systems
- Show design time systems can populate the Design Time control loop catalogue
-DCAE-MOD interacting with the design time catalogue
-SDC interacting with the design time catalogue
- Show TOSCA defined control loops being onboarded and deployed
Longterm Roadmap
"Knowledge" is a key component for automation and control loops.
A common knowledge can be used for Monitor, Analyze, Plan and Execute functions.
In Rel G we want to start to address in a PoC the aspect of the catalogue where multiple ONAP components could be involved in the Design Time phase.
A longterm strategy needs to apply the common "knowledge" concept to the entire Control Loop Lifecycle.
Business Requirements
Participating Companies
Ericsson
AT&T
Contributions in Rel H
Presentation to ARCHCOM: APP LCM_ARCHCOM_REL H_20201201.pdf
Architecture and Design wiki page
Impacts in Rel H
Rel H PoC ticket:
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ARCHCOM ticket:
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PoC is hosted by Policy project
Contributions in Rel G
- Presentation to ARCHCOM (2020/07/14)
- Presentation to SDC project (2020/07/06)
- Presentation to ONAP TSC 2020/07/02 –>ControlLoopTOSCA_DTCatalogue_TSC_2020_07_02.pdf
- Inputs to Control Loop Subcommittee 2020/07/01:
DCAEMOD_CLAMP and Policy interworking_2020_07_01.pptx
- LFN DDF presentation 2020/06/25 → ControlLoopTOSCA_DTCatalogue_DDF_2020_06_25.pptx
- Input to Control Loop Subcommittee 2020/06/17 → DCAEMOD_CLAMP and Policy interworking_2020_06_17_PA2.pptx
- Input to Control Loop Subcommittee 2020/05/13 → DCAEMOD_CLAMP and Policy interworking_2020_05_13.pptx
Impacts in Rel G
Release requirement for this PoC in Rel G: REQ-402
Jira tracking in ARCHCOM: ONAPARC-605
PoC is hosted by CLAMP project
Project | Impact | Notes |
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| CLAMP | Create a TOSCA definition for a Control Loop (and its components) | |
| CLAMP | Create Design Time Catalogue for control loops | |
| CLAMP | Create REST interface towards Design Time Catalogue | |
| CLAMP | Build interaction between SDC and Design Time Catalogue | |
| CLAMP | Build interaction between DCAE-MOD and Design Time Catalogue | |
| CLAMP | Build interaction between Design Time Catalogue and Run Time CLAMP |
Project Commitment
Project
Commitment
Team Calendar
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