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Capability NameCapability ValueGeneric CapabilityDescriptiopnDescription

cpuModelSpecificationBinding

strictBinding

equalOrBetterBinding

(tick)

VDUs may be developed, compiled, optimized or validated on particular CPU models. Some deployments may wish to permit the VDU to be deployed on a platform with the specified CPU only, or with an alternative CPU with the same architecture, instruction set, and if specified, instruction set extensions, or with a CPU of equivalent or greater capability.

instructionSetRequirements

aes, sse, avx, cat, cmt, mbm, ddio, smt, rdrand, etc etc

(tick)

Long list of instruction set extensions.

simultaneousMultiThreading

Enabled

disabled

(tick)

The use of Simultaneous Multi-Threading HW is an efficient way to increase the compute capacity of a platform. SMT HW threads share some CPU core resources. In some VDU implementations, it may be necessary to very explicitly control the HW thread allocation on a platform. This could be to help ensure locality in data caches or as a mechanism to enhance determinism

hypervisorConfiguration

HPET

memoryCompaction

kernelSamepageMerging

(tick)

Long list: High Precision Event Timer configuration, memory compaction, kernel samepage merging, etc.

computeRas

pciDetectedAndCorrectedErrors pciDetectedAndUncorrectedErrors

(tick)

Reliability, Availability, Serviceability (RAS)

Long list of values: pciDetectedAndCorrectedErrors, pciDetectedAndUncorrectedErrors

cpuModel

List of model identifiers


The CPU model for which the VDU has been developed, compiled for, optimized on,  validated on or preferred for some reason.

directIoAccessToCache

Values – TBD


Descriptions related to cache functions – TBD

accelerator

Values – TBD


Descriptions related to accelerator functions – TBD

measuredLaunchEnvironment

Values – TBD


Descriptions related to boot environment functions – TBD

secureEnclave

Values – TBD


Descriptions related to secure region functions – TBD

numVirtualCpu

1-N


Number of virtual CPUs

virtualCpuClock

0-N


Minimum virtual CPU clock rate (e.g. in

MHz). The cardinality can be 0 during the allocation request, if no particular value is requested.

logicalCpuPinningPolicy

dedicated

shared


Determines if CPUs from the host platform should be committed to the VDU or shared between VDUs.

logicalCpuThreadPinningPolicy

require

isolate

prefer


Determines the manner in which CPU (HW) threads are allocated to VDUs. Require means CPU (HW) thread siblings should be allocated

Isolate means allocate CPU (HW) threads from different execution units.

Prefer means ideally allocate CPU HW threads from the same physical execution units but if not available, continue with allocation.

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Capability NameCapability ValueDescriptiopnDescription

storageIops

0..N

Required storage characteristics (e.g. speed), including Key Quality Indicators (KQIs) for performance and reliability/availability

storageResilencyMechanism

Erasure

tripleReplication

Erasure code based back-end, triple replication based back-end for ensuring data resiliency.

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Capability NameCapability ValueDescriptiopnDescription

numberCpu

0..N

Number of CPU cores for this logical node. The cumulative number of CPU requests per node must equal the VDU level numVirtualCpu requirement.

...

Capability NameCapability ValueDescriptiopnDescription

localNumaMemorySize

0..N

The amount of memory that needs to be collocated with this specific logical (NUMA) node.

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Capability NameCapability ValueDescriptiopnDescription

pciVendorId


PCI-SIG vendor ID for the device

pciDeviceId


PCI-SIG device ID for the device

pciNumDevices


Number of PCI devices required.

pciAddress


Geographic location of the PCI device via the standard PCI-SIG addressing model of Domain:Bus:device:function

pciDeviceLocalToNumaNode

required

notRequired

Determines if I/O device affinity is required.

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