Page Comparison

cpuModelSpecificationBinding

strictBinding

equalOrBetterBinding

VDUs may be developed, compiled, optimized or validated on particular CPU models. Some deployments may wish to permit the VDU to be deployed on a platform with the specified CPU only, or with an alternative CPU with the same architecture, instruction set, and if specified, instruction set extensions, or with a CPU of equivalent or greater capability.

instructionSetRequirements

aes, sse, avx, cat, cmt, mbm, ddio, smt, rdrand, etc etc

x

Long list of instruction set extensions.

simultaneousMultiThreading

Enabled

disabledx

The use of Simultaneous Multi-Threading HW is an efficient way to increase the compute capacity of a platform. SMT HW threads share some CPU core resources. In some VDU implementations, it may be necessary to very explicitly control the HW thread allocation on a platform. This could be to help ensure locality in data caches or as a mechanism to enhance determinism

hypervisorConfiguration

HPET

memoryCompaction

kernelSamepageMergingx

Long list: High Precision Event Timer configuration, memory compaction, kernel samepage merging, etc.

computeRas

pciDetectedAndCorrectedErrors pciDetectedAndUncorrectedErrorsx

Reliability, Availability, Serviceability (RAS)

Long list of values: pciDetectedAndCorrectedErrors, pciDetectedAndUncorrectedErrors

cpuModel

List of model identifiers

The CPU model for which the VDU has been developed, compiled for, optimized on,  validated on or preferred for some reason.

directIoAccessToCache

Values – TBDx

Descriptions related to cache functions – TBD

accelerator

Values – TBD

x

x

Descriptions related to accelerator functions – TBD

measuredLaunchEnvironment

Values – TBDx

Descriptions related to boot environment functions – TBD

secureEnclave

Values – TBD

x

Descriptions related to secure region functions – TBD

numVirtualCpu

1-N

x

Number of virtual CPUs

virtualCpuClock

0-N

x

Minimum virtual CPU clock rate (e.g. in

MHz). The cardinality can be 0 during the allocation request, if no particular value is requested.

logicalCpuPinningPolicy

dedicated

sharedx

Determines if CPUs from the host platform should be committed to the VDU or shared between VDUs.

logicalCpuThreadPinningPolicy

require

isolate

preferx

Determines the manner in which CPU (HW) threads are allocated to VDUs. Require means CPU (HW) thread siblings should be allocated

Isolate means allocate CPU (HW) threads from different execution units.

Prefer means ideally allocate CPU HW threads from the same physical execution units but if not available, continue with allocation.

attributeReference

vnfd à vdu à virtualComputeDesc à virtualMemory à vduMemRequirements

N/A

N/A

Assuming the registry entry maps to an attribute the IFA011 or IFA014 specification, the value should give the reader an explicit (ideally fully qualified) reference to that attribute.

schemaVersion

N/A

N/A

Version identifier for the schema

schemaSelector

N/A

Identifier for the particular schema to use.

memoryPageSize

ANY, 4KB, 2MB, 1GBx

Memory page size

numberOfPages

0..NX

Number of pages of this specific page size.

Note, The size of memory requested in all instances of the vduMemRequirements must be less than or equal to the virtualMemSize attribute of the virtualMemoryData information element.

memoryAllocationPolicy

strictLocalAffinity

preferredLocalAffinityx

Strict Local (to node) Affinity or Preferred local (to node) affinity

memoryType

x

Type of memory

memorySpeed

x

Agreed unit of memory speed

memoryRas

ECC, SDDC, thermalThrottling, demandAndPatrolScrubbingx

Long list of memory technologies

memoryBandwidth

0..N

x

Agreed unit of memory bandwidth where 0 is unspecified.

processorCacheAllocationType

Values – TBD

x

Agreed type of processor cache allocation

processorCacheAllocationSize

0..N

x

Agreed unit of processor cach

storageIops

0..Nx

Required storage characteristics (e.g. speed), including Key Quality Indicators (KQIs) for performance and reliability/availability

storageResilencyMechanism

Erasure

tripleReplicationx

Erasure code based back-end, triple replication based back-end for ensuring data resiliency.

numberCpu

0..Nx

Number of CPU cores for this logical node. The cumulative number of CPU requests per node must equal the VDU level numVirtualCpu requirement.

localNumaMemorySize

0..Nx

The amount of memory that needs to be collocated with this specific logical (NUMA) node.

pciVendorId

PCI-SIG vendor ID for the device

pciDeviceId

PCI-SIG device ID for the device

pciNumDevices

x

Number of PCI devices required.

pciAddress

Geographic location of the PCI device via the standard PCI-SIG addressing model of Domain:Bus:device:function

pciDeviceLocalToNumaNode

required

notRequiredx

Determines if I/O device affinity is required.

nicFeature

LSO, LRO, RSS, RDMA

x

Long list of NIC related items such as LSO, LRO, RSS, RDMA, etc.

dataProcessingAccelerationLibray

Dpdk_Version

x

Name and version of the data processing acceleration library required. Orchestration can match any NIC that is known to be compatible with the specified library.

interfaceType

Virtio, PCI-Passthrough, SR-IOV, E1000, RTL8139, PCNETx

Network interface type

vendorSpecificNicFeature

TBA

List of vendor specific NIC related items.